Phase Locked Loops ("PLL's") are systems which allow different signals in different systems to track with one another. One application of a PLL is in digital communication systems. In digital communication systems, the receiving system must be able generate the various frequencies necessary for processing various received signals. For example, a receiving system must be able to synthesize a specific frequency for mixing down the received signals. To accomplish this, a reference frequency is applied to the input of a PLL and a system division ratio of the PLL is set so that the output is some scaled up factor of the input. One problem common to all PLL's is that the output frequency of the PLL system will require a certain amount of time to lock up to a given input frequency. This is known as the lock time. The lock time of a PLL is highly non-linear and very difficult to control. It is desirable to reduce the lock time as much as possible so as to reduce the amount of time the system must wait for the PLL to lock.
Frequency synthesis using a PLL is well known in the art. One example of a prior art PLL frequency synthesizer is shown in FIG. 1. The PLL 100 of FIG. 1 includes a phase detector ("PD") 110, a loop filter 120, a voltage controlled oscillator ("VCO") 130, a reference divider 101 having a divider ratio of R, and a feedback divider 102 having a divider ratio of B. The PLL 100 of FIG. 1 is known as an Integer Divider because the frequency at the output is an integer multiple of the frequency at the input of the phase detector. A fixed reference signal Fref is transmitted to the reference divider 101 and then to one input of the Phase Detector. The output of the VCO is divided by the feedback divider and input to the other input of the Phase Detector. Assuming the system is locked the following equation is satisfied: EQU F1=F2 EQU F1=Fref/R EQU F2=Fout/B
and EQU Fout=Fref (B/R)
By way of example, if Fref=10 Mhz, R=100, and B=5, then EQU Fout=500 kHz
Thus it can be seen that Fout will be some integer fraction of the reference frequency Fref.
Another example of a prior art PLL frequency synthesizer is shown in FIG. 2. The PLL 200 of FIG. 2 includes a phase detector ("PD") 210, a loop filter 220, a voltage controlled oscillator ("VCO") 230, a reference divider 201 having a divider ratio of R, a feedback divider 202 having a divider ratio of B, and a prescaler divider 203 having a divider ratio of K. The PLL 200 of FIG. 2 is known as an Integer Divider with Prescaling. A fixed reference signal Fref is transmitted to the reference divider 201 and then to one input of the phase detector. The output of the VCO is divided by the prescaler divider and the feedback divider, and applied to the other input of the phase detector. Again, assuming the system is locked the following equation is satisfied: EQU F1=F2 EQU F1=Fref/R EQU F2=F3/B EQU F3=Fout/K
and EQU Fout=Fref*K*(B/R)
Therefore, with prescaling, if Fref=10 Mhz, R=100, B=5, K=10, then EQU Fout=5 MHz
Thus it can be seen that Fout will be some integer fraction of the reference frequency Fref multiplied by the prescaler value.
FIG. 3 shows another example of a prior art PLL used for frequency synthesis. The PLL 300 of FIG. 3 includes a phase detector 340, a loop filter 350, a VCO 360, a reference divider 310 having a divider ratio of R, a feedback divider 320 having a divider ratio of B, an auxiliary divider 325 having a divider ratio of A, and a dual modulus prescaler 330 which can be configured to have a divide ratio of either K or K+1. Again the reference frequency is divided down before being applied to the input of the phase detector. The output signal is fed back through the dual modulus prescaler which feeds a signal to both the feedback divider and the auxiliary divider. The output of the feedback divider is applied to the other input of the phase detector.
To understand the operation of the PLL 300 of FIG. 3 by way of example, assume that both the feedback divider and auxiliary divider are DOWN counters, referred to here as B-counter and A-counter respectively. The output of the B-counter is transmitted to the input of the phase detector, and additionally, over LOAD line 301 to the load inputs of both the A-counter and B-counter. Therefore, every time the B-counter counts to zero and outputs a pulse, it will reset both the B-counter and the A-counter to their initial values. The dual modulus prescaler 330 is a divider which can divide the output, Fout, by two different integer values (in this case K and K+1) in accordance with the Prescaler Control line 302 from the A-counter. Assuming the system is locked and the B-counter has just counted down to zero and output a pulse to an input of the phase detector as well as reset the B-counter and A-counter, the signal Fout at the VCO output will be received by the dual modulus prescaler. Initially, the prescaler will divide the VCO output, Fout, by K+1 and the prescaler output will begin to supply pulses to both the B-counter and A-counter, causing each to begin to count down. When the A-counter reaches zero, a signal is transmitted over the Prescaler Control line which causes the dual modulus prescaler to reconfigure itself to stop dividing by K+1 and begin dividing by K. Thereafter, the prescaler will divide the output, Fout, by K and the prescaler output will cause the B-counter to continue to count down until it reaches zero. When the B-counter reaches zero, it outputs another pulse to the input of the phase detector. This pulse also causes the A-counter and B-counter to reset. Therefore, it can be seen that for every pulse, Npd, at the input of the phase detector, there will be Ntot pulses at the output of the VCO. Ntot can be determined by noting that while the A-counter is counting down the prescaler is dividing by K+1. Therefore, the total number of pulses at the VCO output required for the A-counter to count down to zero is A(K+1). Thereafter, the prescaler divides by K, so the total number of pulses at the VCO output required for the B-counter to finish its count down to zero is (B-A)(K) (note: the B-counter and A-counter were counting down together). Therefore, the total number of pulses at the output of the VCO, Ntot, is given by: EQU Ntot=A(K+1)+(B-A) K For one pulse, Npd, into the phase detector. EQU Ntot=A+BK
or in terms of the period, EQU Tpd=Tout (A+BK) EQU Tpd=1/F1 and Tout=1/Fout EQU Fout=F1 (A+BK)
Therefore, the following equations are satisfied: EQU F1=Fref/R=F2=F3/B EQU F3=Fout/(K+1) For A cycles (i.e. while A is counting down) EQU F3=Fout/K For B-A cycles (i.e. while B is counting down after A has finished counting down.
and the VCO output frequency is given by: EQU Fout=(Fref/R)*(A+BK)
It can be seen that a necessary condition of this system is that the B-counter must contain a value which is equal to or larger than the value contained within the A-counter. It can be seen that other implementations besides DOWN counters could be used to implement the system of FIG. 3. Therefore, a more generic condition for the system is that the auxiliary divider must signal the prescaler and become inactive before the B-divider. This type of PLL frequency synthesizer is called a dual modulus prescaler integer PLL.
In many systems it is advantageous to synthesize a frequency which is a non-integer multiple or fraction of a reference frequency. Such frequency synthesizers are called fractional frequency synthesizers and achieve faster phase lock since the reference frequency can be increased. An example of a prior art PLL used as a fractional frequency synthesizer is shown in FIG. 4A. The fractional frequency synthesizer PLL 400 of FIG. 4 includes a phase detector 450, a loop filter 460, a VCO 470, a reference divider 410 having a divider ratio of R, a feedback divider 420 having a divider ratio of N, a pulse swallowing circuit 430, an accumulator ("accumulator") 440, an N-register 425 for storing the integer portion of a system divisor number, and an F-register 445 for storing the fractional portion of a system divisor number. The system division ratio of such a fractional PLL system is N.F, where N is the integer part and F is the fractional part. In other words, Fout=Fref (N.F). The integer and fractional parts of the division ratio are stored in the N-register and F-register, respectively.
To illustrate the operation of the fractional PLL 400, assume the system is locked and that the desired division ratio of the system is: EQU N=5 F=3 and N.F=5.3 EQU Fout=Fref (5.3) for R=1
Therefore, for every 10 cycles of Fref, there will be 53 cycles of Fout. FIG. 4B illustrates the signal F1=Fref (R=1) at the input of the phase detector as well as the contents of the accumulator accumulator. During the first cycle of Fref, referred to here as the first reference cycle, the PLL attempts to divide the output of the VCO, Fout, by N.F=5.3, but this it cannot do. Instead, during the first cycle, the system divides Fout by the integer portion of the fractional divisor, N=5, which is loaded into the feedback divider. Therefore, during the first reference cycle, there is an error between F1 and F2 equal to 0.F * Fout 0.3 * Fout. The error in Fout is going to show up as a phase error in F2 at the input of the phase detector. This phase error can be represented and accounted for by using the accumulator to keep track of the error in Fout. This is accomplished by loading the value of 0.F into the accumulator and using F1 (=Fref in this case) to accumulate the error in each reference cycle. This is shown in FIG. 4B. During the first reference cycle, 0.F=0.3 is loaded into the accumulator. During the next cycle, an additional error of 0.F=0.3 is added to the current error. This continues until the phase error between F1=Fref and F2=Fout/N becomes greater than one full cycle of Fout=N*F2 (i.e., 2.pi. radians of Fout). This corresponds to the point where the fractional error in accumulator becomes greater than unity. As shown in FIGS. 4A and 4B, when the fractional error in the accumulator exceeds unity, an overflow signal ("OVF") in the accumulator signals the pulse swallowing circuit to remove a pulse from the feedback path. The result of removing the pulse is that the feedback divider will not register one pulse of Fout. This is the same as if the feedback divider had divided by N+1=6, rather than by N=5 during that reference cycle, which will essentially delay F2 and reduce the phase error between F1 and F2. A residual error of 0.2 is maintained in the accumulator as shown in FIG. 4B. which represents the phase error between F1 and F2 after the pulse is swallowed. The error will again accumulate with each reference cycle. This process will proceed across 10 reference cycles as shown in FIG. 4B. Note that the accumulator overflows three times during the ten reference cycles. Therefore, over ten reference cycles the VCO has put out 10 * 5 cycles plus three additional pulses which were not transmitted to the feedback divider. In other words, 10 cycles of Fref produced 53 cycles of Fout, or EQU 10*Tref=53*Tout EQU 10/Fref=53/Fout EQU Fout=5.3 Fref EQU Fout=N.F Fref
which is what was desired.
All of the above mentioned PLL frequency synthesizer architectures share problems associated with traditional PLL's. One problem is that at low reference frequencies, the PLL's require a longer time to lock than at high frequencies. For fractional frequency synthesizers, another problem is that at high operating frequencies PLL's have high levels of spurious tone power caused by the averaging and which can reduce system performance.
Accordingly, it would be desirable to have a PLL which could achieve a fast lock time without the spurious tone power resulting from high frequency operation.